From the simulation had been carried out using a Livewire Simulation Software Device, it shows that the circuit is functioning well as follow the Astable Mode Theorem of Analog Integrated Circuit Timer (IC Timer) 555. The concept of the circuit is to generate continuous stream of rectangular pulses having a specified frequency.
Resistor R1 is connected between VCC and the discharge pin (pin 7) and another resistor (R2) is connected between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common node. Hence the capacitor is charged through R1 and R2, and discharged only through R2, since pin 7 has low impedance to ground during output low intervals of the cycle, therefore discharging the capacitor. In the astable mode, the frequency of the pulse stream depends on the values of R1, R2 and C:
The frequency generated from the simulation approximately the same with the frequency calculated by using the astable frequency theory.
From the theory,
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